1. Field of the Invention
The present invention relates to semiconductor memory devices and methods of manufacturing the same, and particularly to a semiconductor memory device, for example, a dynamic random access memory (hereinafter referred to as DRAM) having memory cells comprising a field effect transistor and a capacitor, and a method of manufacturing the same.
2. Description of the Background Art
In recent years, the demand for semiconductor memory devices has been rapidly increased according to the remarkable spread of information equipment such as computers. In addition, functionally, semiconductor memory devices having large-scale storage capacity and capable of high-speed operation are demanded. Under such a background, technical development is in progress with respect to a high degree of integration and high response rate or high reliability of semiconductor memory devices.
Among semiconductor memory devices, there is a DRAM which is capable of random input/output of storage information. Generally, a DRAM is implemented with a memory cell array, which is a storage region for storing a large number of bits of information, and peripheral circuits necessary for entry from and withdrawal to the outside.
FIG. 5 is a block diagram illustrating a structure of a general DRAM. Referring to FIG. 5, a DRAM 50 comprises a memory cell array 51, a row and column address buffer 52, a row decoder 53 and a column decoder 54, a sense refresh amplifier 55, a data in buffer 56 and a data out buffer 57, and a clock generator 58. Memory cell array 51 is for storing a data signal of storage information. Row and column address buffer 52 is for receiving address signals A.sub.0 -A.sub.9 from the outside for selecting a memory cell which constitutes a unit storage circuit. Row decoder 53 and column decoder 54 are for specifying a memory cell by decoding the address signal. Sense refresh amplifier 55 is for amplifying and reading the signal stored in the specified memory cell. Data in buffer 56 and data out buffer 57 are for data input/output. Clock generator 58 generates a clock signal becoming a control signal to each part.
Over more than ten years in the past, the degree of integration of a DRAM implemented as described above has been increased at a speed of approximately four times in three years. There is no sign that this tendency declines after the current four megabit level has been achieved, and it seems to also continue in the future. However, high degree of integration largely depends on miniaturization of memory cells. Because of reduction in capacitance according to miniaturization, problems of soft errors and so on have arisen. In order to solve these problems and secure capacitance larger than a constant value, a memory cell having a structure of a trench-type capacitor formed by etching a semiconductor substrate in a trench shape or a stack-type capacitor stacked on a semiconductor substrate or the like has been developed.
FIG. 6 is a partial plan view illustrating a planar arrangement of memory cells of a DRAM comprising stack-type capacitors, for example shown in Japanese Patent Publication No. 60-2784 (1985). FIG. 7 is a diagram illustrating an equivalent circuit of four bits of the memory cells constituting the memory cell array shown in FIG. 6. The memory cell array comprises a plurality of word lines WL extending parallel in the row direction and a plurality of bit line pairs BL, BL extending parallel in the column direction. Referring to FIGS. 6 and 7, memory cells C.sub.00, C.sub.01 are provided in the vicinity of the crossings of word lines WL.sub.00, WL.sub.01 and bit line BL.sub.00. Memory cells C.sub.02, C.sub.03 are provided in the vicinity of the crossings of word lines WL.sub.02, WL.sub.03 and bit line BL.sub.00. The capacitor of each memory cell is implemented with a lower electrode E.sub.00, an upper electrode E.sub.01, and an oxide film (not shown in FIG. 6) between these electrodes. In FIG. 6, bit lines BL.sub.00, BL.sub.00 are connected via a contact hole CH to an impurity diffusion region of a semiconductor substrate. In FIG. 7, a pair of bit lines BL.sub.00, BL.sub.00 are arranged parallel with each other in regard to a sense amplifier SA. Such an arrangement of bit lines are referred to as a folded bit line type. The sense amplifier SA is for detecting and amplifying a signal from each memory cell C.
FIG. 8 is a partial sectional view illustrating a sectional structure taken along the line VIII--VIII in FIG. 6. Referring to FIG. 8, a structure of a memory cell of a DRAM comprising a conventional stack-type capacitor will be described.
A field oxide film 32 as an element isolation region is formed on a prescribed surface of a p-type silicon semiconductor substrate 31. An island region as an element formation region is electrically isolated by field oxide film 32. In the island region, n.sup.+ source/drain regions 33, 34 are formed so as to have a prescribed space between them. A channel region 35 is formed between n.sup.+ source/drain regions 33 and 34. A gate oxide film, 36 is formed on channel region 35. A gate electrode (word line WL.sub.01) 37 comprising a polysilicon layer is formed on gate oxide film 36 so as to extend in a direction crossing at right angles the direction of the channel length of the channel region 35. An interlayer oxide film 38 is formed so as to coat the surface of gate electrode 37. A word line (WL.sub.02) 39 comprises a polysilicon layer and is formed on field oxide film 32. An interlayer oxide film 40 is formed so as to coat the surface of a word line (WL.sub.02) 39.
A capacitor lower electrode (E.sub.00) 41 comprising a polysilicon layer is formed so as to be in contact with n.sup.+ source/drain region 34. In addition, capacitor lower electrode 41 is formed so as to extend on field oxide film 32, and formed on gate electrode 37, with interlayer oxide film 38 interposed, and on word line 39, with interlayer oxide film 40 interposed. An interlayer oxide film 42 is formed so as to coat the surface of capacitor lower electrode (E.sub.00) 41. A capacitor upper electrode (a plate electrode)(E.sub.01) 43 comprising a polysilicon layer is formed so as to be opposed to the surface of capacitor lower electrode (E.sub.00) 41 with interlayer oxide film 42 interposed.
A PSG film 44 is formed on the whole surface of p-type silicon semiconductor substrate 31 so as to coat the capacitor implemented as described above. A contact hole (CH) 45 is opened in PSG film 44 so as to expose the surface of n.sup.+ source/drain region 33. A bit line (BL.sub.00) 46 is connected via contact hole (CH) 45 to n.sup.+ source/drain region 33. Bit line 46 comprises a metal layer including aluminum and is formed so as to extend in a direction along the direction of the channel length of channel region 35.
A conventional memory cell 47 is implemented as described above. According to the structure of this memory cell, a part of capacitor lower electrode 41 and capacitor upper electrode 43 extends, curving, up to above gate electrode 37 and word line 39. As a result, it is possible to enlarge the area of the capacitor and to secure capacitance larger than a constant value.
In conventional memory cell 47 as described above, however, capacitor lower electrode 41 and capacitor upper electrode 43 are formed, being stacked on the surface of p-type silicon semiconductor substrate 31. This causes the step between the upper surface of PSG film 44, as an insulating layer coating capacitor lower electrode 41 and capacitor upper electrode 43, and the surface of p-type silicon semiconductor substrate 31 to become larger. Consequently, the aspect ratio of contact hole 45 for connecting bit line 46 to n.sup.+ source/drain region 33 increases. The increase in the aspect ratio degrades completeness of coating the surface of PSG film in contact hole 45 by bit line 46. Accordingly, there was a problem that disconnection of the bit line tends to happen inside contact hole 45 and reliability of the semiconductor memory device is degraded.
In addition, there was a problem that a photolithography process with extremely high precision is necessary for forming contact hole 45 having a high aspect ratio as described above, and it involves a technical difficulty in manufacturing.
Furthermore, in the conventional memory cell 47 as described above, gate electrode (word line) 37 is also miniaturized as the degree of integration is increased. Accordingly, there was a possibility that the resistance increases when current flows in gate electrode 37, and a response to a signal is delayed. Therefore, it was necessary to attempt to further increase the speed without delaying the response to the signal.
It was also necessary to obtain a structure of a memory cell in which capacitance of a capacitor can be sufficiently secured in order to further advance miniaturization of a memory cell.